Contemporary high performance computing main memory systems are generally composed of one or more dynamic random access memory (DRAM) devices. DRAM devices typically include memory cells arranged in horizontal grids with row and column decoding logic to access values stored at specific addresses. These devices may be physically assembled on a dual in-line memory module (DIMM). The DIMM may provide simple upgrade or maintenance capabilities based on the ease of insertion and removal of the DIMM structure.
Overall computer system performance is affected by each of the key elements of the computer structure, including the performance/structure of the processor(s), any memory cache(s), the input/output (I/O) subsystem(s), the efficiency of the memory control function(s), the main memory device(s), and the type and structure of the memory interconnect interface(s).
Extensive research and development efforts are invested by the industry, on an ongoing basis, to create improved and/or innovative solutions to maximizing overall system performance and density by improving the memory system/subsystem design and/or structure. High-availability systems present further challenges as related to overall system reliability due to customer expectations that new computer systems will markedly surpass existing systems in regard to mean-time-between-failure (MTBF). Other frequent customer requirements further exacerbate the memory system design challenges, and include such items as ease of upgrade and reduced system environmental impact (such as space, power and cooling).
In an effort to make the systems more reliable, a new DIMM structure has made a debut. The non-volatile dual in-line memory module (NVDIMM) may use a combination of DRAM and non-volatile memory, such as NAND flash memory. The NVDIMM may provide a very fast interface for accesses by the system processor and a non-volatile memory that operates at a much slower data rate for data protection.
A state-of-the art flash-backed memory module stores the contents of the DRAM segment into an on-board flash memory during a power-loss event. However, the flash write speed is considerably slower than that of DRAM read speed. Therefore, various methods are needed to manage this backup procedure efficiently. This includes such things as either wider flash bus or lower clock speed or a combination of both. However, memories such as DDR3, used on the majority of new computer systems, have a delay-locked-loop (DLL) that does not run at slow speeds.
A method is required to keep the DRAM operational at low clock speeds. Thus, a need still remains for a non-volatile dynamic random access memory system with non-delay-locked-loop mode in order to simplify the interface between the high speed DRAM and the slower non-volatile memory. In view of the extreme need for data reliability in many of today's computer systems, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.